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NXP Semiconductors /MIMXRT1062 /CCM /CCSR

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Interpret as CCSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PLL3_SW_CLK_SEL_0)PLL3_SW_CLK_SEL

PLL3_SW_CLK_SEL=PLL3_SW_CLK_SEL_0

Description

CCM Clock Switcher Register

Fields

PLL3_SW_CLK_SEL

Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes.

0 (PLL3_SW_CLK_SEL_0): pll3_main_clk

1 (PLL3_SW_CLK_SEL_1): pll3 bypass clock

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data